Within integrated circuits, semiconductor devices such as memory cells including their components are becoming smaller. The smaller components are needed in a memory cell such as those in a static-random-access memory (SRAM). As the size of a SRAM cell decreases, the operational speed of the SRAM typically increases, the power consumption typically decreases, and yields generally increase. Still, the smaller SRAM cell has its problems. The amount of charge at a storage node is about the product of the capacitance of the storage node and the voltage difference between the plates of the storage node capacitor. The smaller SRAM cell typically has less capacitance because the area of the storage node capacitor typically decreases with the SRAM cell size. The decrease in capacitance may allow alpha particles to cause soft errors.
Incorporating additional capacitors within a SRAM cell is one way to increase the storage node capacitance, which typically reduce soft error rate of the SRAM cell. Capacitors that are connected to the storage nodes are discussed in many patents and technical articles. A dynamic-random-access memory (DRAM) typically has a storage capacitor such as a fin capacitor. Many DRAM storage capacitors including fin capacitors are complex and would require many additional processing steps to an existing SRAM process.
In another attempt to reduce soft error rates, a SRAM cell may have its storage nodes capacitively coupled to a relatively constant voltage supply such as V.sub.SS, V.sub.DD, or a fraction of V.sub.DD. One of the capacitor plates typically lies over at least the storage node area of one of the gate electrodes of the latch transistors and lies over part of the field or active area beyond the latch gates. As used in this specification, storage node area is defined as the memory cell area (as seen from a top view of the memory cell) occupied by a contact between 1) one section of a load resistor and a gate electrode of a latch transistor or 2) a source or drain region of a load transistor and a gate electrode of a latch transistor. The capacitor plate may interfere with the placement of contacts or interconnecting lines within the memory cell. Misalignment of the capacitor plates may cause variation in the amount of charge that may be stored by the capacitor. Also, the misalignment of the capacitor plates may also increase the chances of an undesired open or short circuit. Therefore, a larger memory cell area may be required. In a SRAM cell where the relatively constant voltage supply is not V.sub.SS or V.sub.DD, an additional interconnect line may be required to connect to one of the capacitor plates. The placement of contacts or other interconnecting lines may be affected by the additional interconnecting line and typically results in a larger memory cell area if contacts or other interconnecting lines are affected.